Two-wire power transmitting/receiving device and its method

ABSTRACT

When power is supplied from a power transmitting side device  1 , a FET  103  is turned ON and +12V direct current of a power source  101  is supplied to respective power receiving side devices. When transmission data is transmitted from the power transmitting side device  1 , +5V direct current of a power source  201 - 1  is supplied to a terminal a, and a transistor  104  is turned ON/OFF due to a pulse-like voltage change of the transmission data, whereby the transmission data becomes a pulse-like 0V +5V output waveform, and is output to the respective power receiving side devices. When the power transmitting side device  1  receives reply data from the power receiving side device, the power receiving side device changes a voltage to a 3.5V +5V pulse as reply data. A photocoupler  105  detects the voltage change, whereby the power transmitting side device  1  receives the reply data from the power receiving side device.

TECHNICAL FIELD

[0001] The present invention relates to power transmitting/receivingcommunication methods and apparatus, and more particularly, relates to atwo-wire power transmitting/receiving communication method and apparatusfor performing power transmission/reception and intercommunicationsusing two power transmission wires.

BACKGROUND ART

[0002] Conventionally, as a two-wire power transmission method forperforming power transmission/reception and intercommunications usingtwo power transmission wires, there is a high-frequency superimpositionmethod for superimposing a high-frequency signal onto the transmissionwires for power transmission. In the high-frequency superimpositionmethod, a power receiving side device includes a high-frequency bandpassfilter, thereby detecting only a high-frequency signal. Also, a methodfor superimposing a phase-modulated pulse signal onto DC twotransmission wires for power transmission, and a method for causing oneof DC two-wires to be interrupted or shorted out at regular intervals,thereby performing pulse-like transformation for direct power for powertransmission, are also known.

[0003] On the other hand, in Japanese Patent Examined Publication No.S54-40304, a method for performing time-shared power transmission ofpower and a signal is disclosed. This method is a method fortransmitting the power and the signal over a pair of transmission wiresby performing time-shared power transmission of the power and the signalfrom a power transmitting side: The power is then smoothed by acondenser, etc., so as to be a direct current, a logic circuit and arelay drive circuit, etc., are activated, and the power and the signalare demultiplexed by detecting their differences in width and height,etc., in a power receiving side. Compared to the above-describedhigh-frequency superimposition method, or the like, this method canrealize power transmission/reception and communications at low cost witha simple circuit. Also, as a method for performing time-shared powertransmission of the power and the signal, a method enablingbi-directional communications capable of specifying which powerreceiving side device processes the signal, by assigning an address to asignal to be transmitted, or capable of identifying a transmitting sidewhich has transmitted the signal is also known.

[0004] However, the above-described high-frequency superimpositionmethod has to use a complicated circuit structure and high-cost circuitparts for modulation in order to improve signal leakage and noiseimmunity, thereby increasing costs. Also, the above-described method forperforming superimposition for a phase-modulated pulse signal for powertransmission has a limit in a transmission speed, and the method forcausing one of DC two-wires to be interrupted or shorted out at regularintervals has a problem that there is always noise, whereby both methodsdo not allow many power receiving side devices to be connected from theaspect of transmission efficiencies. Furthermore, as for theabove-described method for performing time-shared power transmission forthe power and the signal, a signal from the power transmitting sidecannot be distinguished from a signal from the power receiving sidebased on a voltage, etc., and the power receiving side has to receiveall signals from the power transmitting side and all signals fromanother power receiving side, and determine whether or not these areeffective data addressed thereto, thereby complicating a process andincreasing a burden in the power receiving side. As a result, a cost ofsoftware, etc., performing a process at the power receiving side isincreased.

[0005] Therefore, an object of the present invention is to provide alow-cost and transmission-efficient two-wire powertransmitting/receiving communication apparatus and method, which reducea processing burden of the power receiving side.

DISCLOSURE OF THE INVENTION

[0006] To achieve the above objects, the present invention has thefollowing aspects.

[0007] A first aspect of the present invention is directed to a powertransmitting/receiving communication apparatus for performing powersupply and intercommunications between a power transmitting side deviceand at least one power receiving side device, which are interconnectedvia two power transmission wires, wherein

[0008] the power transmitting side device includes:

[0009] a power transmitting side power source section for outputtingpower having a first power level;

[0010] a power transmitting side data processing section for generatingtransmission data giving an instruction to the power receiving sidedevice, and receiving and processing reply data from the power receivingside device;

[0011] a power transmitting side period control section for performingtime-sharing control for a period of supplying the power, a datatransmission period of transmitting the transmission data, and a replydata reception period of receiving the reply data; and

[0012] a power transmitting side synthesis section for supplying thepower having the first power level, which is output from the powertransmitting side power source section, to the power transmission wireduring the power supply period, converting the transmission data intotransmission data having a second power level for transmission to thepower transmission wire during the data transmission period, and furthertransmitting, to the power transmission wire, a data reception signalhaving a power level different from the first power level during thereply data reception period, and

[0013] the power receiving side device includes:

[0014] a power receiving side power source section for storing the powerhaving the first power level, which is supplied via the powertransmission wire;

[0015] a power receiving side data processing section for receiving andprocessing the transmission data having the second power level from thepower transmitting side device, and generating the reply data making areply to the power transmitting side device;

[0016] a power receiving side transmitting section for converting thereply data output from the power receiving side data processing sectioninto reply data having a third power level for replying to the powertransmission wire, during the reply data reception period; and

[0017] a power level detection section for detecting a power level ofthe power transmission wire, and outputting power level detectionresults to the power receiving side data processing section, and

[0018] the power receiving side data processing section selects andreceives data from the power transmission wire, based on the power leveldetection results from the power level detection section, and furtheroutputs the reply data to the power receiving side transmitting sectionby detecting reception of the data reception signal.

[0019] Based on the above-described structure of the present invention,it is possible to perform time-shared transmission/reception of a powersupply to the power receiving side device and communication data betweenthe power transmitting side device and the power receiving side device.Further, it is possible for a power receiving side device to distinguisha type of data based only on level detection, by setting power levels ofthe transmission data from the power transmitting side device and thereply data from the power receiving side device at different levels,thereby selecting unnecessary data by a hardware-related process andreducing a processing burden of the CPU. As a result, a software processof the power receiving side device is simplified, and a cost of softwarecan be reduced. Also, the power receiving side device can determine atiming of transmitting the reply data from the power transmitting sidedevice, by detecting a voltage of the data reception signal, whereby itis possible to detect the timing and transmit the reply data when thepower transmitting side device requests.

[0020] The above-described power receiving side data processing sectionis preferably characterized by selecting and receiving data having thesecond power level from the power transmission wire, based on the powerlevel detection results from the power level detection section. Thus,the power receiving side device identifies the reply data from anotherpower receiving side device by only voltage detection, and does notreceive the data, thereby selecting unnecessary data by ahardware-related process and reducing a processing burden of the CPU. Asa result, a software process of the power receiving side device issimplified, and a cost of software can be reduced.

[0021] The power transmitting side data processing section is preferablyfurther characterized by attaching an address of the power receivingside device to the transmission data, as an address of a target to beinstructed, and the power receiving side data processing section ischaracterized by processing only data having an address thereto, whichis attached to the transmission data. Thus, the power transmitting sidedevice can specify the power receiving side device processing thetransmission data by attaching an address of the power receiving sidedevice to the data to be transmitted, thereby reducing an process of thepower receiving side device which does not require reception of theabove-described data.

[0022] Also, the power receiving side data processing section ispreferably characterized by further attaching an address thereof as atransmission source for making a reply. Thus, the power receiving sidedevice replying by the reply data can be identified, whereby it ispossible to identify the reply data of each power receiving side deviceand perform processing in a data process of the power transmitting sidedevice.

[0023] The power transmitting side data processing section is preferablycharacterized by further attaching an identification code shared by allthe power receiving side devices, which are connected to the powertransmission wire, as an address of a target to be instructed, and allthe power receiving side data processing sections connected to the powertransmission wire are characterized by processing the transmission datain accordance with the identification code attached to the transmissiondata. Thus, the power transmitting side device can give an instruction,with a piece of transmission data, to all the power receiving sidedevices connected by the power transmission wire, thereby reducing aprocess of transmitting the transmission data.

[0024] A second aspect of the present invention is directed to a powerreceiving communication device, which is supplied with power from apower transmitting side device connected via two power transmissionwires, for performing intercommunications with the power transmittingside device, comprising:

[0025] a power receiving side power source section for storing powerhaving a first power level, which is supplied from the powertransmitting side device via the power transmission wire;

[0026] a power receiving side data processing section for receiving andprocessing transmission data having a second power level from the powertransmitting side device, and generating the reply data making a replyto the power transmitting side device;

[0027] a power receiving side transmitting section for converting thereply data output from the power receiving side data processing sectioninto reply data having a third power level for replying to the powertransmission wire, during a reply data reception period, in which thepower transmitting side device performs time-sharing and transmits adata reception signal having a power level different from the firstpower level; and

[0028] a power level detection section for detecting a power level ofthe power transmission wire and outputting power level detection resultsto the power receiving side data processing section, wherein

[0029] the power receiving side data processing section selects andreceives data from the power transmission wire, based on the power leveldetection results from the power level detection section, and furtheroutputs the reply data to the power receiving side transmitting sectionby detecting reception of the data reception signal.

[0030] The power receiving side data processing section is preferablycharacterized by selecting and receiving data having the second powerlevel from the power transmission wire based on the power leveldetection results from the power level detection section.

[0031] A third aspect of the present invention is directed to a powertransmitting communication device for performing power supply andintercommunications with at least one power receiving side deviceconnected via two power transmission wires, comprising:

[0032] a power transmitting side power source section for outputtingpower having a first power level to the power receiving side device;

[0033] a power transmitting side data processing section for generatingtransmission data giving an instruction to the power receiving sidedevice, and receiving and processing reply data from the power receivingside device;

[0034] a power transmitting side period control section for performingtime-sharing control for a period of supplying the power, a datatransmission period of transmitting the transmission data, and a replydata reception period of receiving the reply data; and

[0035] a power transmitting side synthesis section for supplying thepower having the first power level, which is output from the powertransmitting side power source section, to the power transmission wireduring the power supply period, converting the transmission data intotransmission data having a second power level for transmission to thepower transmission wire during the data transmission period, andtransmitting, to the power receiving side device, a data receptionsignal having a power level different from the first power level via thepower transmission wire during the reply data reception period, wherein

[0036] the power transmitting side data processing section distinguishesthe reply data having a third power level from other power levels forreception.

[0037] A fourth aspect of the present invention is directed to a powertransmitting/receiving communication method for performing power supplyand intercommunications between a device on a power transmitting sideand at least one device on a power receiving side, which areinterconnected via two power transmission wires, comprising:

[0038] on the power transmitting side,

[0039] a power transmitting side power supplying step of outputtingpower having a first power level;

[0040] a power transmitting side data processing step of generatingtransmission data giving an instruction to the power receiving sidedevice, and receiving and processing reply data from the power receivingside device;

[0041] a power transmitting side period controlling step of performingtime-sharing control for a period of supplying the power, a datatransmission period of transmitting the transmission data, and a replydata reception period of receiving the reply data; and

[0042] a power transmitting side synthesis step of supplying the powerhaving the first power level, which is output from the powertransmitting side power source section, to the power transmission wireduring the power supply period, converting the transmission data intotransmission data having a second power level for transmission to thepower transmission wire during the data transmission period, andtransmitting, to the power transmission wire, a data reception signalhaving a power level different from the first power level, during thereply data reception period, and

[0043] on the power receiving side,

[0044] a power receiving side power storing step of storing the powerhaving the first power level, which is supplied via the powertransmission wire;

[0045] a power receiving side data processing step of receiving andprocessing the transmission data having the second power level from thepower transmitting side device, and generating the reply data replyingto the power transmitting side device;

[0046] a power receiving side transmitting step of converting the replydata output from the power receiving side data processing section intoreply data having a third power level for replying to the powertransmission wire, during the reply data reception period, and

[0047] a power level detecting step of detecting a power level of thepower transmission wire and outputting power level detection results tothe power receiving side data processing section, wherein

[0048] the power receiving side data processing step selects andreceives data from the power transmission wire based on the power leveldetection results by the power level detecting step, and further outputsthe reply data to the power receiving side transmitting step bydetecting reception of the data reception signal.

[0049] The power receiving side data processing step is preferablycharacterized by selecting and receiving data having the second powerlevel from the power transmission wire based on the power leveldetection results by the power level detecting step.

[0050] The power transmitting side data processing step is preferablycharacterized by further attaching an address of a receiving side as anaddress of a target to be instructed, and the power receiving side dataprocessing step is characterized by processing only data having anaddress thereto, which is attached to the transmission data.

[0051] Also, the power receiving side data processing step is preferablycharacterized by further attaching an address thereof as a transmissionsource for making a reply.

[0052] The power transmitting side data processing step is preferablycharacterized by further attaching an identification code shared by anentire power receiving side, which is connected to the powertransmission wire, as an address of a target to be instructed, and theentire power receiving side connected to the power transmission wire ischaracterized by processing the transmission data in accordance with theidentification code attached to the transmission data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053]FIG. 1 is a block diagram illustrating the basic structure of apower transmitting/receiving communication apparatus according to anembodiment of the present invention.

[0054]FIG. 2 is a block diagram illustrating the functional structure ofa power transmitting side device in the power transmitting/receivingcommunication apparatus according to the embodiment of the presentinvention.

[0055]FIG. 3 is a block diagram illustrating the functional structure ofa power receiving side device in the power transmitting/receivingcommunication apparatus according to the embodiment of the presentinvention.

[0056]FIG. 4 is a circuit diagram of a circuit included in the powertransmitting side device in the power transmitting/receivingcommunication apparatus according to the embodiment of the presentinvention.

[0057]FIG. 5 is a circuit diagram of a circuit included in the powerreceiving side device in the power transmitting/receiving communicationapparatus according to the embodiment of the present invention.

[0058]FIG. 6 is a flowchart showing an operation of the powertransmitting side device in the power transmitting/receivingcommunication apparatus according to the embodiment of the presentinvention.

[0059]FIG. 7 is a flowchart showing a sub-routine of step S111 of FIG.6.

[0060]FIG. 8 is a flowchart showing an operation of the power receivingside device in the power transmitting/receiving communication apparatusaccording to the embodiment of the present invention.

[0061]FIG. 9 is a flowchart showing a sub-routine of step S307 of FIG.8.

[0062]FIG. 10 is an illustration showing power transmission andcommunication data, which is performed between the power transmittingside device and the power receiving side device in the powertransmitting/receiving communication apparatus according to theembodiment of the present invention, by a relationship between a voltagechange and time.

BEST MODE FOR CARRYING OUT THE INVENTION

[0063]FIG. 1 is a block diagram illustrating the basic structure of apower transmitting/receiving communication apparatus according to anembodiment of the present invention. Hereinafter, using FIG. 1, theembodiment will be described.

[0064] In FIG. 1, a power transmitting side device land a plurality ofpower receiving side devices 2-1˜n are interconnected by a pair oftransmission wires 3 a and 3 b. The power transmission wire 3 a couplesa terminal a of the power transmitting side device 1 to terminals c-1˜nof the respective power receiving side devices 2-1˜n, and the powertransmission wire 3 b couples a terminal b of the power transmittingside device 1 to terminals d-1˜n of the respective power receiving sidedevices 2-1˜n. By those transmission wires 3 a and 3 b, power issupplied to the power receiving side devices 2-1˜n from the powertransmitting side device 1, and communication is performed between thepower transmitting side device 1 and the power receiving side devices2-1˜n.

[0065]FIG. 2 is a block diagram illustrating the functional structure ofthe power transmitting side device 1 in the power transmitting/receivingcommunication apparatus. Note that FIG. 2 is an illustration showingonly a functional block related to the present invention forsimplification of descriptions. Hereinafter, using FIG. 2, thefunctional structure of the power transmitting side device 1 will bedescribed.

[0066] In FIG. 2, the power transmitting side device 1 includes a CPU10, a power and transmission data synthesis circuit 11, a reply datareceiving circuit 12, a power source circuit 13, a display section 14,an input section 15, and a memory 16. The CPU 10 generates transmissiondata to the power receiving side device 2 and processes reply data fromthe power receiving side device 2. Also, the CPU 10 adjusts a processingtiming in order to perform time-shared processing of power supply to thepower receiving side device 2, transmission of the transmission data,and reception of the reply data. Furthermore, the CPU 10 outputs, to thedisplay section 14, contents to be sent to a user, and performs aprocess based on contents input from the input section 15 in the casewhere there is an instruction from the user. Based on the timingadjusted by the CPU 10, the power and transmission data synthesiscircuit 11 amplifies and transmits the transmission data to the powerreceiving side device 2 if transmission data from the CPU 10 to thepower receiving side device 2 is output, and supplies power from thepower source circuit 13 to the power receiving side device 2 if a powersupply instruction is output. The reply data receiving circuit 12extracts the reply data transmitted from the power receiving side device2, and outputs it to the CPU 10. Note that, typically, a display devicesuch as a liquid crystal display, etc., is used as the display section14, and a device such as a keyboard or a numeric keypad, etc., is usedas the input section 15.

[0067]FIG. 3 is a block diagram illustrating the functional structure ofthe power receiving side device 2 in the power transmitting/receivingcommunication apparatus. Note that FIG. 3 is an illustration showingonly a functional block related to the present invention forsimplification of descriptions. Hereinafter, using FIG. 3, thefunctional structure of the power receiving side device 2 will bedescribed.

[0068] In FIG. 3, the power receiving side device 2 includes a CPU 20, apower and transmission data separation circuit 21, a reply datatransmission circuit 22, an internal power source circuit 23, a voltagedetection section 24, a display section 25, an input section 26, and amemory 27. The CPU 20 generates reply data to the power transmittingside device 1 and processes the transmission data from the powertransmitting side device 1. Also, the CPU 20 outputs the data generatedby the CPU 20 in accordance with a reply data transmission timingadjusted by the power transmitting side device 1. Furthermore, the CPU20 outputs, to the display section 25, contents to be sent to the user,and performs a process based on contents input from the input section 26in the case where there is an instruction or data from the user. Thepower and transmission data separation circuit 21 separates power andtransmission data supplied from the power transmitting side device 1,and outputs the power and the transmission data to the internal powersource circuit 23 and the CPU 20, respectively. The reply datatransmission circuit 22 outputs, from the CPU 20 to the powertransmitting side device 1, the reply data to be transmitted from thepower receiving side device 2 to the power transmitting side device 1.The voltage detection section 24 detects a voltage input or outputto/from the power receiving side device 2, determines a type of input oroutput data based on the voltage, and outputs the results to the CPU 20.Note that, typically, a display device such as a liquid crystal displayor a number display, etc., is used as the display section 25, and adevice such as a switch, a sensor, or a scanner, etc., is used as theinput section 26.

[0069] Next, a circuit structure of the CPU 10, the power andtransmission data synthesis circuit 11, the transmission data receivingcircuit 12, and the power source circuit 13, which are included in thepower transmitting side device 1, will be described. Note that FIG. 4 isa circuit diagram of a circuit structured between the CPU 10 of thepower transmitting side device 1 and the power transmission wires 3.Hereinafter, using FIG. 4, a circuit of the power transmitting sidedevice 1 is described.

[0070] In FIG. 4, a power transmitting side circuit is structuredbetween the CPU 10 of the power transmitting side device 1 and theterminal a. In the power transmitting side circuit, a +12V power source101, and +5V power sources 102-1 and 102-2, a field effect transistor103 (hereinafter, referred to as FET), a transistor 104, a photocoupler105, a diode 106, a constant current circuit 107, and resistors 108-1˜5are provided. Note that the terminal b is a GND line and is connected toground in the power transmitting side device 1.

[0071] In the FET 103, a terminal I/O1 of the CPU 10, the power source101, and the terminal a, are coupled to a gate, a source, and a drain,respectively. Also, in the transistor 104, via the resistor 108-2 andthe resistor 108-1, respectively, a terminal T×D of the CPU 10 and theterminal a are coupled to a base and a collector, respectively, and anemitter is grounded. Furthermore, in the photocoupler 105, the powersource 102-2 are coupled to a collector via a terminal R×D of the CPU 10and the resistor 108-5, and an emitter is grounded. Also, in thephotocoupler 105, the terminal a is coupled to the cathode side, and thepower source 102-1 is coupled to the anode side via the constant currentcircuit 107 and the diode 106. Note that the resistor 108-4 is coupledin parallel to a diode section of the photocoupler 105, and the resistor108-3 is coupled in parallel to the constant current circuit 107 and theresistor 108-4.

[0072] First, in the case where power is supplied from the powertransmitting side device 1 to the power receiving side device 2, the CPU10 outputs, from the terminal I/O1, a signal for turning the FET 103 ON.The FET 103 is turned ON by the signal, whereby +12V direct current ofthe power source 101 is applied to the terminal a, and supplied to therespective power receiving side devices 2 via the power transmissionwire 3.

[0073] Next, in the case where transmission data is transmitted from thepower transmitting side device 1 to the power receiving side device 2,the CPU 10 turns output from the terminal I/O1 OFF, whereby +12V directcurrent is turned OFF, and +5V direct current of the power source 102-1is supplied to the terminal a. Then, the CPU 10 outputs pulse-liketransmission data from the terminal T×D (the structure of thetransmission data will be described below). The transistor 104 is turnedON/OFF due to a pulse-like voltage change of the transmission data,whereby the voltage of the terminal a is 0V when the transistor 104 isON, and the voltage of the terminal a is +5V when the transistor 104 isOFF. That is, the voltage of the terminal a is changed in accordancewith the transmission data, whereby the transmission data is output, asa pulse-like 0V

+5V output waveform, to the respective power receiving side devices 2via the power transmission wire 3.

[0074] On the other hand, in the case where the power transmitting sidedevice 1 receives the reply data from the power receiving side device 2,+5V direct current is supplied to the terminal a in the same manner asdescribed above. After detecting the supply of the +5V direct current,the power receiving side device 2 changes its voltage into a +3.5V

+5V pulse as reply data (an operation of the power receiving side device2 will be described below). When the voltage of the terminal a becomes+3.5V, the voltage on the cathode side of the photocoupler 105 becomes+3.5V, whereby current passes through the diode section of thephotocoupler 105 due to occurrence of a potential difference between theanode side and the cathode side of the photocoupler 105. By thiscurrent, the transistor section of the photocoupler 105 enters an ONstate, and the voltage of the terminal R×D of the CPU 10 becomes 0V. Onthe other hand, when the voltage of the terminal a is +5V, there is nopotential difference between the anode side and the cathode side of thephotocoupler 105, whereby no current passes through the diode section ofthe photocoupler 105. Thus, the transistor section of the photocoupler105 enters an OFF state, and the voltage of the terminal R×D of the CPU10 becomes +5V. By inputting the above-described voltage change of theterminal R×D, the CPU 10 receives the reply data from the powerreceiving side device 2.

[0075] Next, a circuit structure of the CPU 20, the power andtransmission data separation circuit 21, the reply data transmissioncircuit 22, the internal power source circuit 23, and the voltagedetection section 24, which are included in the power receiving sidedevice 2, will be described. Note that FIG. 5 is a circuit diagram of acircuit structured between the CPU 20 of the power receiving side device2 and the power transmission wire 3. Hereinafter, using FIG. 5, acircuit of the power receiving side device 2 is described.

[0076] In FIG. 5, a power transmitting side circuit is structuredbetween the CPU 20 of the power receiving side device 2 and the terminalc. In the power transmitting side circuit, an +5V internal power source201, a voltage detection section 202, a regulator 203, a condenser 204,a diode 205, a transistor 206, and resistors 207-1˜4 are provided. Notethat the terminal d is a GND line, and connected to ground in the powerreceiving side device 2.

[0077] The regulator 203 has one end coupled to the power source 201 andthe other end coupled to the condenser 204 and the diode 205. Also, theother end of the condenser 204 is grounded, and the other end of thediode 205 is coupled to the terminal c. Also, in the transistor 206, aterminal T×D of the CPU 20 is coupled to a base via the resistor 207-1and the terminal c is coupled to a collector via the resistor 207-2, andan emitter is grounded. Furthermore, the resistor 207-3 has one endcoupled to the terminal c and the other end coupled to the resistor207-4, the voltage detection section 202, and the terminal R×D of theCPU 20. Also, the other end of the resistor 207-4 is grounded, and thevoltage detection section 202 is coupled to a terminal IN of the CPU 20.

[0078] First, in the case where power is supplied from the powertransmitting side device 1 to the power receiving side device 2, asdescribed above, +12V direct current is supplied to the terminal c aspower via the power transmission wire 3. The +12V direct current isstored in the condenser 204 after passing through thebackflow-preventing diode 205. Also, the +12V direct current, which alsopasses through the regulator 203, is transformed into +5V direct currentand supplied to the power source 201. The power source 201 is used as anoperation power source of the power receiving side device 2; and the+12V stored in the condenser 204 is transformed into +5V by theregulator 203 and supplied as an operation power source in the casewhere +12V direct current, which will be described below, is notsupplied.

[0079] Note that the +12V direct current supplied from the terminal c isdivided by the resistors 207-3 and 207-4, and received by the voltagedetection section 202. The voltage detection section 202 determines,based on a pre-set reference value, whether or not the above-describeddivided voltage is greater than the above-described reference value, andoutputs the results to the terminal IN of the CPU 20. In the CPU 20,based on the results from the voltage detection section 202, thedetermination is made that the voltage of the terminal c is a supplyvoltage, whereby no data is received from the terminal R×D of the CPU20.

[0080] Next, when the power receiving side device 2 receivestransmission data from the power transmitting side device 1, asdescribed above, the transmission data is input to the terminal c in thepower receiving side device 2 as a 0V

+5V pulse-like voltage change, via the power transmission wire 3. Thetransmission data is divided by the resistors 207-3 and 207-4, andreceived by the voltage detection section 202. As described above, basedon the pre-set reference value, the voltage detection section 202determines whether or not the divided voltage is greater than thereference value, and outputs the results to the terminal IN of the CPU20. In the CPU 20, based on the results from the voltage detectionsection 202, the determination is made that the transmission data fromthe power transmitting side device 1 is input to the terminal c, and thetransmission data is received from the terminal R×D of the CPU 20. Notethat the transmission data is a 0V

+5V pulse-like voltage change, and does not pass through the diode 205due to the +12V stored in the condenser 204.

[0081] Next, when the reply data is transmitted from the power receivingside device 2 to the power transmitting side device 1, as describedabove, the +5V direct current is supplied to the terminal c via thepower transmission wire 3. The +5V direct current is divided by theresistors 207-3 and 207-4, and received by the voltage detection section202. As described above, based on the pre-set reference value, thevoltage detection section 202 determines whether or not theabove-described divided voltage is greater than the pre-set referencevalue, and outputs the results to the terminal IN of the CPU 20. In theCPU 20, based on the results from the voltage detection section 202, thedetermination is made that transmission of the reply data is instructedby the power transmitting side device 1, and the pulse-like reply datais output from the terminal T×D (the structure of the reply data will bedescribed below). The transistor 206 is turned ON/OFF due to apulse-like voltage change of the reply data, whereby the voltage of theterminal c becomes +3.5V when the transistor 206 is ON (a resistancevalue of the resistor 207-2 is previously adjusted, whereby the voltageof the terminal c in the ON state of the transistor 206 is adjusted soas to become +3.5V), and the voltage of the terminal c becomes +5V whenthe transistor 206 is OFF. That is, the voltage of the terminal c ischanged in accordance with the above-described reply data, whereby theabove-described reply data is output, as a pulse-like +3.5V

+5V output waveform, to the power transmitting side device 1 via thepower transmission wire 3.

[0082] Next, an operation of the power transmitting side device 1 willbe described. Note that FIG. 6 is a flowchart showing the operation ofthe power transmitting side device 1, and FIG. 7 is a flowchart showinga sub-routine of step S111 of FIG. 6. Hereinafter, using FIGS. 6 and 7,the operation of the power transmitting side device 1 will be described.

[0083] In FIG. 6, the power transmitting side device 1 supplies, via thepower transmission wire 3, +12V direct current as power of the powerreceiving side device 2 (step S101). This power supply is continueduntil the amount of power required for an operation of the respectivepower receiving side devices 2 coupled to the power transmission wire 3is stored, whereby, in this case, a charge time is set in accordancewith the power receiving side device 2 whose requiring amount of poweris the greatest, and the power supply is continued until the charge timehas elapsed (step S102). Next, the CPU 10 determines whether or not onemessage of transmission data to the power receiving side device 2 iscompleted (step S103). When one message of transmission data iscompleted, the CPU 10 turns the +12V power supply OFF (step S104),subsequently turns +5V direct current output ON, and holds the +5Vduring a time 5 μs (step S105). Next, the CPU 10 obtains one byte ofdata from the above-described one message of transmission data, andtransmits it to the power transmission wire 3 (step S106).

[0084] This transmission data includes an integer multiple of one byte,and is capable of individually specifying the power receiving sidedevice 2 corresponding to a transmission destination by an address.Furthermore, it is also possible to specify, as the transmissiondestination, an identification code shared by all the power receivingside devices 2 as the transmission destination. Also, data indicating ahead of the one message (hereinafter, referred to as STX data) and dataindicating an end of the one message (referred to as ETX data) areattached to the first byte of the transmission data and the last byte ofthe transmission data, respectively, and a start bit and a stop bit areattached to each byte of data.

[0085] Then, the CPU 10 determines whether or not the above-describedone message of transmission data has been completely transmitted bydetecting, for example, the ETX data (step S107). If some transmissiondata is remaining at step S107, the CPU 10 goes back to step S106, andtransmits one byte of data from the remaining transmission data. On theother hand, if all the transmission data is transmitted at step S107,the CPU 10 turns output, which is turned ON at step S105, of +5V directcurrent OFF (step S108), and turns +12V direct current power supply ON(step S109). Next, the CPU 10 determines whether or not the transmissiondata at step S103 requests reply data from the destination powerreceiving side device 2 (step S110). If the determination is made atstep S110 that the reply data is requested, the CPU 10 performs aprocess for receiving reply data from the power receiving side device 2(step S111). If the determination is made at step S110 that the replydata is not requested, the CPU 10 continues the +12V power supply.

[0086] In FIG. 7, the above-described process for receiving reply datafrom the power receiving side device 2 at step S111 is described. First,the CPU 10 determines whether or not +12V power supply exceeds theabove-described pre-set charge time required for power storage of therespective power receiving side devices 2 (step S201). Until a lapse ofthe above-described charge time, the CPU 10 continues the +12V powersupply. If the above-described charge time has elapsed, the +12V powersupply is turned OFF (step S202), and output of +5V direct current isturned ON (step S203). Next, the CPU 10 waits for reply data from thepower receiving side device 2 (step S204), and determines whether or nota start bit, which is attached to the beginning of one byte of replydata, is detected (step S205). If the determination is made that thestart bit is detected, the CPU 10 determines whether or not one byte ofreply data has been completely received (step S206), and continuesreceiving until one byte of reply data is finalized. If thedetermination is made at step S206 that one byte of reply data isreceived, the CPU 10 determines whether or not the received reply datahas completely received one message, based on the above-described ETXdata, for example (step S207). If the determination is made at step S207that the received reply data is incomplete, the CPU 10 goes back to stepS204, and continues waiting for the reply data. Next, if thedetermination is made at step S207 that the received reply data hascompletely received one message, the CPU 10 turns output of +5V directcurrent OFF (step S208), and turns +12V power supply ON (step S209).Then, the CPU 10 performs a process for the reply data (step S210), andends the reply data receiving process.

[0087] On the other hand, if the start bit is not detected at step S205,the CPU 10 determines whether or not an elapsed time from step S203 islonger than the pre-set time (step S211). If the above-described elapsedtime is shorter than the pre-set time, the CPU 10 goes back to stepS204, and continues waiting for data. If the above-described elapsedtime is longer than the pre-set time, the CPU 10 determines that it is areply error of the power receiving side device 2, turns output of +5Vdirect current OFF (step S212), turns +12V power supply ON (step S 213),and performs a reply error process such as a request to retransmit replydata according to a type of data requesting a reply (step S214).

[0088] Next, an operation of the power receiving side device 2 will bedescribed. Note that FIG. 8 is a flowchart showing the operation of thepower receiving side device 2, and FIG. 9 is a flowchart showing asub-routine of step S307 of FIG. 8. Hereinafter, using FIGS. 8 and 9,the operation of the power receiving side device 2 is described.

[0089] In FIG. 8, the power receiving side device 2 detects, in thevoltage detection section 202, a voltage of the power transmission wire3 (step S301). In the voltage detection section 202, the determinationis made, in a pre-set voltage range, whether or not the voltage of thepower transmission wire 3 is +5V (step S302), and whether or not it is+12V (step S309), and an output corresponding to the respective cases isoutput to the CPU 20.

[0090] If the determination is made at step S302 that the voltage of thepower transmission wire 3 is +5V, the CPU 20 determines that data is tobe transmitted from the power transmitting side device 1 or anotherpower receiving side device 2. Furthermore, the voltage detectionsection 202 detects a voltage range of the received pulse-like data,detects whether or not a voltage range of the data is 0V

+5V based on a pre-set voltage range in similar manners as describedabove (step S303), and outputs the results to the CPU 20. If the voltagerange of the received data is 0V

+5V, the CPU 20 determines that it is transmission data from the powertransmitting side device 1, and receives the transmission data from theterminal R×D (step S304). Next, the CPU 20 determines whether or not onebyte of transmission data is received (step S305). If the determinationis made at step S305 that one byte of transmission data is received, theCPU 20 determines whether or not one message of the receivedtransmission data has been completely received, based on the ETX data,for example (step S306). If the determination is made at steps S305 andS306 that the received transmission data is incomplete, the CPU 20 goesback to step S304, and continues receiving the transmission data. Next,if the determination is made at step S306 that one message of thereceived transmission data has been completely received, the CPU 20performs a process for the received transmission data (step S307).

[0091] On the other hand, if the data is not 0V

+5V at step S303 (for example, pulse-like +3.5

+5V data), the CPU 20 determines that it is reply data, etc., fromanother power receiving side device 2 to the power transmitting sidedevice 1, and does not receive data from the power transmission wire 3(step S308).

[0092] Also, if the determination is made at step S309 that the voltageof the power transmission wire 3 is +12V, and hence that it is powersupply from the power transmitting side device 1, the CPU 20 does notperform reception from the power transmission wire 3 to the CPU 20 (stepS310), and stores power in the internal power source circuit 23 of thepower receiving side device 2 (step S311). Note that if thedetermination is made at step S309 that the voltage of the powertransmission wire 3 is not +12V, the voltage detection section 202continues detecting of the voltage of the power transmission wire 3.

[0093] In FIG. 9, the process for receiving transmission data from thepower transmitting side device 1 as aforementioned at step S307 isdescribed. First, the CPU 20 determines whether or not the transmissiondata is addressed thereto based on an address, etc., indicating adestination of the transmission data (step S401). If the transmissiondata is not addressed thereto, the CPU 20 deletes the transmission data(step S408), and ends the process. If the transmission data is addressedthereto, the CPU 20 performs a process corresponding to the transmissiondata (step S402). Then, the CPU 20 determines whether or not thetransmission data requests reply data to the power transmitting sidedevice 1 (step S403). If the transmission data does not request replydata, the CPU 20 ends the transmission data receiving process.

[0094] On the other hand, if the transmission data requests reply dataat step S403, the voltage detection section 202 detects the voltage ofthe power transmission wire 3 in order to detect a timing oftransmitting the reply data from the power receiving side device 2 (stepS404). The voltage detection section 202 determines the voltage of thepower transmission wire 3 based on a pre-set voltage range, and outputs,to the CPU 20, an output corresponding to each case. The CPU 20determines whether or not the voltage of the power transmission wire 3is +5V based on a signal from the voltage detection section 202 (stepS405), and continues detecting the voltage until the voltage of thepower transmission wire 3 becomes +5V. If the determination is made atstep S405 that the voltage of the power transmission wire 3 has become+5V, the CPU 20 transmits one byte of reply data to the powertransmitting side device 1 (step S406).

[0095] As is the case with the above-described transmission data, thisreply data also includes an integer multiple of one byte, and is capableof attaching an individual address of the power receiving side device 2corresponding to a transmission source. Also, an STX data and an ETXdata are attached to the first one byte of the reply data and the lastone byte of the reply data, respectively, and a start bit and a stop bitare attached to each one byte of data.

[0096] Next, the CPU 20 determines whether or not all the reply data hasbeen transmitted (step S407). If the reply data is remaining, the CPU 20goes back to step S406, and continues transmitting the reply data. Ifall the reply data is transmitted, the CPU 20 ends the process.

[0097] Note that, in the flowchart of FIG. 9, the power receiving sidedevice 2 transmits the reply data at step S406 after the processcorresponding to the reply data of step S402. However, in accordancewith the contents of a process performed by the CPU 20, steps S402 andS406 may be performed simultaneously, or a process at step S402 may becontinuously performed.

[0098] Next, power supply and communication data performed between thepower transmitting side device 1 and the power receiving side device 2will be described. Note that FIG. 10 is an illustration showing powertransmission and communication data, which is performed between thepower transmitting side device 1 and the power receiving side device 2,by a relationship between a voltage change and time. FIG. 10(a) shows acase in which the power transmitting side device 1 does not requestreply data from the power receiving side device 2, and FIG. 10(b) showsa case in which the power transmitting side device 1 requests reply datafrom the power receiving side device 2. Hereinafter, using FIG. 10, arelationship between a voltage change and time will be described.

[0099]FIG. 10(a) is an illustration showing a power which is suppliedand data which is transmitted/received, between the power transmittingside device 1 and the power receiving side device 2 via the powertransmission wire 3, in which a horizontal axis indicates time and avertical axis indicates a voltage, in a case where the powertransmitting side device 1 does not request reply data from the powerreceiving side device 2. In FIG. 10(a), during an interval A1, +12Vdirect current is first supplied to the power transmission wire 3 fromthe power transmitting side device 1. Here, the interval A1 is continuedlonger than the charge time corresponding to the power receiving sidedevice 2 whose requiring amount of power storage is the greatest. Then,the power transmitting side device 1 supplies +5V direct current to thepower transmission wire 3 for 5 μs during an interval T in order tonotify the respective power receiving side devices 2 of transmission ofthe transmission data. Then, the power transmitting side device 1transmits n bytes of transmission data during corresponding intervalsD1˜n. The voltages of the respective data D1˜n are changed from 0V

+5V like a pulse, and a head bit of each data D1˜n indicates a startbit. Also, data D1, which is a first byte of the transmission data, isthe STX data indicating a head of one message of data, asaforementioned, and data Dn is the ETX data indicating an end of onemessage of data. After the completion of transmission of thetransmission data, the power transmitting side device 1 supplies +12Vdirect current to the respective power receiving side devices 2 duringan interval A2.

[0100]FIG. 10(b) is an illustration showing a power which is suppliedand data which is transmitted/received, between the power transmittingside device 1 and the power receiving side device 2 via the powertransmission wire 3, in which a horizontal axis indicates time and avertical axis indicates a voltage, in a case where the powertransmitting side device 1 requests reply data from the power receivingside device 2. In FIG. 10(b), the intervals A1˜Dn are the same asabove-described FIG. 10(a), with the descriptions thereof omitted. Asdescribed above, during the interval A2, the power transmitting sidedevice 1 continues +12V power supply longer than the charge timecorresponding to the power receiving side device 2 whose requiringamount of power storage is the greatest. Then, during an interval U, thepower transmitting side device 1 supplies +5V direct current to thepower transmission wire 3 in order to urge the power receiving sidedevice 2 to transmit the reply data. The power receiving side device 2transmitting the reply data detects +5V, and transmits m bytes of dataR1˜Rm. The respective data R1˜m have a pulse-like +3.5V

+5V voltage change, and a head bit of each data R1˜m indicates a startbit. Also, data R1, which is a first byte of the reply data, is the STXdata indicating a head of one message of data, as aforementioned, anddata Rm is the ETX data indicating an end of one message of data. Afterthe completion of reception of the reply data, the power transmittingside device 1 supplies +12V direct current to the respective powerreceiving side devices 2 during an interval A3.

[0101] Note that, in the present embodiment, it is assumed that a supplyvoltage to the respective power receiving side devices 2 is +12V, avoltage of the transmission data transmitted from the power transmittingside device 1 is 0V

+5V, and a voltage of the reply data transmitted from the powerreceiving side device 2 is +3.5V

+5V, but those voltages are not limited thereto. As long as theabove-described power supply, the above-described transmission data, andthe above-described reply data can be distinguished by detecting avoltage, any voltage can realize the present powertransmitting/receiving communication apparatus.

[0102] As such, in the power transmitting/receiving communicationapparatus according to the present invention, it is possible to performtime-shared transmission/reception of a power supply to the powerreceiving side device, and communication data between the powertransmitting side device and the power receiving side device, and it isalso possible to perform bi-directional communications capable ofspecifying the power receiving side device processing transmission data,or identifying the power receiving side device replying the reply data,by assigning data to be transmitted/received with an address of thepower receiving side device. Furthermore, by setting different voltagesfor the transmission data from the power transmitting side device andthe reply data from the power receiving side device, the power receivingside device can identify the reply data from another power receivingside device by only detecting a voltage, thereby selecting unnecessarydata by a hardware-related process and reducing a processing burden ofthe CPU. As a result, a software process of the power receiving sidedevice is simplified, and a cost of software can be reduced. As aresult, a software process of the power receiving side device issimplified, and a cost of software can be reduced.

[0103] Industrial Applicability

[0104] As described above, the present invention, which is low in costand transmission-efficient, allows a processing burden of the receivingside to be reduced in a power transmitting/receiving communicationapparatus and method, more particularly, in a two-wire powertransmitting/receiving communication apparatus and method using twopower transmission wires for performing power transmission/reception andintercommunications.

1. (Amended) A power transmitting/receiving communication apparatus inwhich power supply and intercommunications are performed between a powertransmitting side device and at least one power receiving side device,which are interconnected via two power transmission wires, wherein thepower transmitting side device includes: a power transmitting side powersource section for outputting power having a first power level; a powertransmitting side data processing section for generating transmissiondata giving an instruction to the power receiving side device, andreceiving and processing reply data from the power receiving sidedevice; a power transmitting side period control section for performingtime-sharing control for a period of supplying the power, a datatransmission period of transmitting the transmission data, and a replydata reception period of receiving the reply data; and a powertransmitting side synthesis section for supplying the power having thefirst power level, which is output from the power transmitting sidepower source section, to the power transmission wire during the powersupply period, converting the transmission data into transmission datahaving a second power level for transmission to the power transmissionwire during the data transmission period, and further transmitting, tothe power transmission wire, a data reception signal having a powerlevel different from the first power level during the reply datareception period, and the power receiving side device includes: a powerreceiving side power source section for storing the power having thefirst power level, which is supplied via the power transmission wire; apower receiving side data processing section for receiving andprocessing the transmission data having the second power level from thepower transmitting side device, and generating the reply data making areply to the power transmitting side device; a power receiving sidetransmitting section for converting the reply data output from the powerreceiving side data processing section into reply data having a thirdpower level for replying to the power transmission wire, during thereply data reception period; and a power level detection section fordetecting a power level of the power transmission wire, and outputtingpower level detection results to the power receiving side dataprocessing section, and the power receiving side data processing sectionselects and receives data from the power transmission wire, based on thepower level detection results from the power level detection section,and further outputs the reply data to the power receiving sidetransmitting section by detecting reception of the data receptionsignal.
 2. The power transmitting/receiving communication apparatusaccording to claim 1, wherein the power receiving side data processingsection selects and receives data having the second power level from thepower transmission wire, based on the power level detection results fromthe power level detection section.
 3. (Deleted)
 4. The powertransmitting/receiving communication apparatus according to claim 1,wherein the power transmitting side data processing section furtherattaches an address of the power receiving side device to thetransmission data, as an address of a target to be instructed, and thepower receiving side data processing section processes only data havingan address thereto, which is attached to the transmission data.
 5. Thepower transmitting/receiving communication apparatus according to claim1, wherein the power receiving side data processing section furtherattaches an address thereof as a transmission source for making a reply.6. The power transmitting/receiving communication apparatus according toclaim 1, wherein the power transmitting side data processing sectionfurther attaches an identification code shared by all the powerreceiving side devices, which are connected to the power transmissionwire, as an address of a target to be instructed, and all the powerreceiving side data processing sections connected to the powertransmission wire process the transmission data in accordance with theidentification code attached to the transmission data.
 7. (Amended) Apower receiving communication device, which is supplied with power froma power transmitting side device connected via two power transmissionwires, for performing intercommunications with the power transmittingside device, comprising: a power receiving side power source section forstoring power having a first power level, which is supplied from thepower transmitting side device via the power transmission wire; a powerreceiving side data processing section for receiving and processingtransmission data having a second power level from the powertransmitting side device, and generating the reply data making a replyto the power transmitting side device; a power receiving sidetransmitting section for converting the reply data output from the powerreceiving side data processing section into reply data having a thirdpower level for replying to the power transmission wire, during a replydata reception period, in which the power transmitting side deviceperforms time-sharing and transmits a data reception signal having apower level different from the first power level; and a power leveldetection section for detecting a power level of the power transmissionwire and outputting power level detection results to the power receivingside data processing section, wherein the power receiving side dataprocessing section selects and receives data from the power transmissionwire, based on the power level detection results from the power leveldetection section, and further outputs the reply data to the powerreceiving side transmitting section by detecting reception of the datareception signal.
 8. The power receiving communication device accordingto claim 7, wherein the power receiving side data processing sectionselects and receives data having the second power level from the powertransmission wire based on the power level detection results from thepower level detection section.
 9. (Deleted)
 10. (Amended) A powertransmitting communication device for performing power supply andintercommunications with at least one power receiving side deviceconnected via two power transmission wires, comprising: a powertransmitting side power source section for outputting power having afirst power level to the power receiving side device; a powertransmitting side data processing section for generating transmissiondata giving an instruction to the power receiving side device, andreceiving and processing reply data from the power receiving sidedevice; a power transmitting side period control section for performingtime-sharing control for a period of supplying the power, a datatransmission period of transmitting the transmission data, and a replydata reception period of receiving the reply data; and a transmittingside synthesis section for supplying the power having the first powerlevel, which is output from the power transmitting side power sourcesection, to the power transmission wire during the power supply period,converting the transmission data into transmission data having a secondpower level for transmission to the power transmission wire during thedata transmission period, and transmitting, to the power receiving sidedevice, a data reception signal having a power level different from thefirst power level via the power transmission wire during the reply datareception period, wherein the power transmitting side data processingsection distinguishes the reply data having a third power level fromother power levels for reception.
 11. (Deleted)
 12. (Amended) A powertransmitting/receiving communication method for performing power supplyand intercommunications between a device on a power transmitting sideand at least one device on a power receiving side, which areinterconnected via two power transmission wires, comprising: on thepower transmitting side, a power transmitting side power supplying stepof outputting power having a first power level; a power transmittingside data processing step of generating transmission data giving aninstruction to the power receiving side device, and receiving andprocessing reply data from the power receiving side device; a powertransmitting side period controlling step of performing time-sharingcontrol for a period of supplying the power, a data transmission periodof transmitting the transmission data, and a reply data reception periodof receiving the reply data; and a power transmitting side synthesisstep of supplying the power having the first power level, which isoutput from the power transmitting side power source section, to thepower transmission wire during the power supply period, converting thetransmission data into transmission data having a second power level fortransmission to the power transmission wire during the data transmissionperiod, and transmitting, to the power transmission wire, a datareception signal having a power level different from the first powerlevel during the reply data reception period, and on the power receivingside, a power receiving side power storing step of storing the powerhaving the first power level, which is supplied via the powertransmission wire; a power receiving side data processing step ofreceiving and processing the transmission data having the second powerlevel from the power transmitting side device, and generating the replydata making a reply to the power transmitting side device; a powerreceiving side transmitting step of converting the reply data outputfrom the power receiving side data processing section into reply datahaving a third power level for replying to the power transmission wire,and a power level detecting step of detecting a power level of the powertransmission wire and outputting power level detection results to thepower receiving side data processing section, wherein the powerreceiving side data processing step selects and receives data from thepower transmission wire based on the power level detection results bythe power level detecting step, and further outputs the reply data tothe power receiving side transmitting step by detecting reception of thedata reception signal.
 13. The power transmitting/receivingcommunication method according to claim 12, wherein the power receivingside data processing step selects and receives data having the secondpower level from the power transmission wire based on the power leveldetection results by the power level detecting step.
 14. (Deleted) 15.The power transmitting/receiving communication method according to claim12, wherein the power transmitting side data processing step furtherattaches an address of a receiving side as an address of a target to beinstructed, and the power receiving side data processing step processesonly data having an address thereto, which is attached to thetransmission data.
 16. The power transmitting/receiving communicationmethod according to claim 12, wherein the power receiving side dataprocessing step further attaches an address thereof as a transmissionsource for making a reply.
 17. The power transmitting/receivingcommunication method according to claim 12, wherein the powertransmitting side data processing step further attaches anidentification code shared by an entire power receiving side, which isconnected to the power transmission wire, as an address of a target tobe instructed, and the entire power receiving side connected to thepower transmission wire processes the transmission data in accordancewith the identification code attached to the transmission data.